Multiple-Valued Logic Buses for Reducing Bus Size, Transitions and Power in Deep Submicron Technologies

In this paper, we explore the potential of bus interconnection models using the Multiple-Valued Logic paradigm to reduce the power consumption of on-chip address and data buses within embedded SoC platforms. Data is sent over the buses using radix-r number system, i.e. ternary, balanced ternary or quaternary, rather than binary. This allows more compact bus design with less number of bus lines. Reducing the number of bus lines also allows us to increase the distance between the adjacent bus lines using the same silicon area. This further reduces interwire capacitance and may lead to significant onchip bus power reduction for embedded SoCs designed with deep sub-micron technology. We also analyze the bus switching activity on on-chip address and data buses operating in radix-r number system, and observe that the number of bus transitions in a radix-r bus, particularly in a quaternary bus, is significantly less than the number of bus transitions in a binary bus. Thus, this results in significant power savings in the total on-chip bus power. Our experimental results show that the radix-r bus models replacing 32-bit binary equivalent can provide up to 61% reduction in the address bus power and up to 58% reduction in the data bus power when compared to a binary bus model. Thus, on-chip radix-r bus models can be alternative to the binary one in power-efficient embedded systems.